The present invention is related to a manufacturing method for a liquid crystal display (LCD) unit, and more particularly to a manufacturing method for an in-plane switching mode liquid crystal display (LCD) unit.
As the technique is developing, it is the trend that the liquid crystal display (LCD) takes the place of the conventional picture tube display and becomes the main stream in the market. Please refer to FIG. 1(a). FIG. 1(a) is a diagram illustrating the circuit of a pixel unit in a liquid crystal display according to the prior art. It is composed of a display unit 12, a storage capacitor 13, and a switching unit accomplished by a thin film transistor 11. Regarding the structure of the display unit 12, it is mainly divided into two types at present. The common structure is a twisted nematic liquid crystal display (TN-LCD), as shown in FIG. 1(b). In FIG. 1(b), the data electrode 121 and the common electrode 122 are mounted at both sides of the liquid crystal molecule 123. The cell gap between the upper and lower glasses is xe2x80x9cd.xe2x80x9d Through controlling the potential difference between the data electrode 121 and the common electrode 122 (the direction of the electric field is shown in a dotted line in the diagram), the liquid crystal molecule 123 can stand erect to form the included angle between the liquid crystal molecule 123 and the Z-axis. Therefore, the light-pervious rate will follow to be changed according to the included angle and the pixel brightness can be controlled. However, due to the rotation way of the liquid crystal molecule in the above display unit structure, the distribution of plural refractions is very different while the watcher has different visual angles, for example, in the inclined directions of Axe2x80x94Axe2x80x2 and Bxe2x80x94Bxe2x80x2 (as shown in FIG. 1(b)). Besides, the pervious rate will be very different and the disadvantage that the bigger visual angle cannot be provided will be existed. Therefore, the above display unit structure has its limitation indeed, especially that the superficial size of the display panel is getting increased at the present time.
Compared with the second type structure (TN-LCD), the first type structure (TN-LCD) has the disadvantage that the rotation way of the liquid crystal molecule has a smaller visual angle. On the contrary, the display unit structure 12 in the second type has a better range of visual angle. Please refer to FIG. 1(c). FIG. 1(c) is a diagram illustrating the display unit structure 12 of an in-plane switching mode (IPS mode) according to the prior art. It is clear in the diagram that the data electrode 121 and the common electrode 122 are mounted at the same side of the liquid crystal molecule 123. Therefore, while the potential difference between the data electrode 121 and the common electrode 122 is changed (the direction of the electric field is shown in a dotted line in the diagram), the liquid crystal molecule 123 will take Z-axis as the axle center and rotate around it. The light-pervious rate will follow to be changed and the pixel brightness control will be accomplished. The rotation way of the liquid crystal molecule in this kind of display unit structure will not have a light-pervious rate change while the watcher has different visual angles. Therefore, it has the advantage that a bigger visual angle can be provided, and it will help a lot for manufacturing the display panel with bigger size.
Please refer to FIGS. 2(a) and 2(b). FIG. 2(a) is a top view showing the pixel unit structure of the in-plane switching mode (IPS mode) in the first conventional thin film transistor LCD according to the prior art. FIG. 2(b) is a sectional view along the A-B line segment showing the pixel unit structure of the in-plane switching mode (IPS mode) in the first conventional thin film transistor LCD according to the prior art. The pixel unit structure is accomplished by the following process:
(a) forming a first mental layer on the substrate 20 and defining thereon a gate line 21, a common electrode 22 of the display unit, and a wiring pad 23 needed for the periphery (the first photo etching process (PEP)).
(b) depositing a gate insulation layer 24, a semi-conductive layer, and a relatively high doped semi-conductive layer, and additionally, defining a channel structure 25(the second photo etching process (PEP)).
(c) forming a second mental layer and defining a source/drain electrode region 26 of thin film transistor, a data line 27, and pixel electrode 28 of the display unit (the third photo etching process (PEP)).
(d) depositing a passivation layer 29 and defining a contact window 231 on the wiring pad 23 (the fourth photo etching process (PEP)).
It is clear in FIGS. 2(a) and 2(b) that the common electrode 22 and pixel electrode 28 of the display unit are respectively accomplished from the first mental layer and the second mental layer, which forms two flats with different altitudes. Therefore, the curve of the data voltage and the pervious rate is asymmetric, as shown in FIG. 2(c). Besides, the display image will have the drawbacks of image-sticking and flicker. Since the common electrode 22 and pixel electrode 28 of the display unit are respectively accomplished from the first mental layer and the second mental layer in two different photo etching processes, the two electrodes will unavoidably have the problem of misalignment, which will cause uneven light-pervious rate and mura.
In order to improve the above drawbacks, another conventional pixel unit structure is developed, as shown in FIG. 3. FIG. 3(a) is a top view showing the pixel unit structure of the in-plane switching mode (IPS mode) in the second conventional thin film transistor LCD according to the prior art. FIG. 3(b) is a sectional view along the A-B line segment showing the pixel unit structure of the in-plane switching mode (IPS mode) in the second conventional thin film transistor LCD according to the prior art. The pixel unit structure is accomplished by the following process:
(a) forming a first mental layer on the substrate 30 and defining thereon a gate line 31, a common electrode 32 of the display unit, a lower electrode 320 for storing capacitance, and a wiring pad 33 needed for the periphery (the first photo etching process (PEP)).
(b) depositing a gate insulation layer 34, a semi-conductive layer, and a relatively high doped semi-conductive layer, and additionally, defining a channel structure 35(the second photo etching process (PEP)).
(c) forming a second mental layer and defining a source/drain electrode region 36 of thin film transistor, a data line 37, and an upper electrode 38 for storing capacitance (the third photo etching process (PEP)).
(d) depositing a passivation layer 39 and respectively defining contact windows 331, 381, and 321 on the wiring pad 33, the upper electrode 38 for storing capacitance, and the common electrode 32 (the fourth photo etching process (PEP)).
(e) forming a third mental layer and defining two comb-shaped electrodes 382 and 322 to have electric contact with the upper electrode 38 and the common electrode 32 through the contact windows 381 and 321 respectively (the fifth photo etching process (PEP)).
It is known from the above description that the two comb-shaped electrodes 382 and 322 are accomplished at the flats with same altitudes in the same photo etching process. Since there is no altitude difference between the two comb-shaped electrodes 382 and 322, it will not result in the problem of misalignment. Although the drawback of the former technique is solved, however, the steps of the photo etching process (PEP) are too many, which will lower the yield efficiency and increase the cost. Hence, how to rectify the foresaid conventional drawback has become the main purpose of the present invention.
It is an object of the present invention to provide a manufacturing method for an in-plane switching mode liquid crystal display (LCD) unit with reduced steps of the photo etching process (PEP).
It is another object of the present invention to provide a manufacturing method for an in-plane switching mode liquid crystal display (LCD) unit to reduce the manufacturing cost and increase the yield efficiency.
According to the present invention, a manufacturing method for in-plane switching mode liquid crystal display (LCD) unit includes steps of: providing a substrate, forming a first conductive layer on said substrate; patterning said first conductive layer to form a gate line, a comb-shaped first electrode, a wiring pad, and a comb-shaped second electrode by a first photo etching process (PEP), forming a first insulation layer and a first semi-conductive layer on said substrate in sequence; patterning said first insulation layer and said first semi-conductive layer to form a channel, an insulation structure, a dielectric layer for storing capacitance, and plural crossed-conductive line insulation structures by a second photo etching process (PEP), forming a second semi-conductive layer and a second conductive layer on said substrate; patterning said second semi-conductive layer and said second conductive layer to form a source/drain electrode, a data line, a connecting electrode, and a first electrode for storing capacitance by a third photo etching process (PEP), wherein said data line covers said crossed-conductive line insulation structure thereon and connects said drain electrode, said connecting electrode is connected between said source electrode and said comb-shaped second electrode, and said first electrode for storing capacitance covers said dielectric layer for storing capacitance thereon and connects said comb-shaped second electrode; and forming a passivation layer on said substrate except partial region of said wiring pad.
In accordance with the present invention, the step of forming a passivation layer further comprises the step of: patterning said passivation layer by a fourth photo etching process (PEP), wherein said passivation layer having a wiring hole on said wring pad.
Preferably, the step of forming a passivation layer further comprises the step of: forming said passivation structure on said substrate except partial region of said wiring pad by a mask deposition method to generate a wiring hole on said wring pad.
Preferably, the substrate is a glass substrate pervious to light.
Preferably, the first conductive and said second conductive layer are made of a material selected from a group consisted of chromium, molybdenum, tantalum molybdate, tungsten molybdate, tantalum, aluminum, aluminum silicide, copper and the combination thereof.
Preferably, the gate insulation layer is made of a material selected from of a group consisted of silicon nitride (SiNX), silicon oxide (SiOX), silicon oxynitride (SiOXNY), tantalum oxide (TaOX), aluminum oxide (AlOX) and the combination thereof.
Preferably, the first semi-conductive layer is made of a material selected from of a group consisted of intrinsic amorphous silicon, intrinsic micro-crystalline silicon, and intrinsic polycrystalline silicon.
Preferably, the second semi-conductive layer is made of a material selected from of a group consisted of N-typed highly doped amorphous silicon, N-typed highly doped micro-crystalline silicon, P-typed highly doped micro-crystalline silicon, N-typed highly doped polycrystalline silicon, and P-typed highly doped polycrystalline silicon.
Preferably, the passivation structure is made of a material selected from of a group consisted of silicon nitride (SiNX), silicon oxide (SiOX), and silicon oxynitride (SiOXNY).
Preferably, the comb-shaped first electrode structure has a comb-shaped structure crossly and parallelly mounted between a comb-shaped structure of said comb-shaped second electrode.
Preferably, the dielectric layer for storing capacitance covers thereon a lower electrode under an storage capacitor of said comb-shaped common electrode structure.
Preferably, the second semi-conductive layer has relatively high doped than first semi-conductive layer.
Preferably, the comb-shaped first electrode is a comb-shaped common electrode.
Preferably, the comb-shaped second electrode is a comb-shaped pixel electrode.